Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8 years of experience in ASIC physical design.
- Experience with ASIC physical design flows and methodologies (i.e. synthesis, place and route, STA, formal verification, CDC, power analysis, etc.).
- Scripting experience in Python, TCL or Perl.
About the job
Experience in extraction of design parameters, QOR metrics, and analyzing trends.
- Experience solving physical design challenges across various technologies such as embedded processors, DDR, networking fabrics, etc.
- Experience in IP integration (memories, IO’s and Analog IP).
- Experience with leading one or more aspects of physical design.
- Working knowledge of semiconductor device physics and transistor characteristics.
- Working knowledge of Verilog/System Verilog.
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a Silicon Physical Design Engineer on the chip implementation team, you will work on the physical implementation of ASICs using advanced technology nodes. You will perform technical evaluations of vendors, process nodes and IP and will provide recommendations. You will work with architecture, logic design and DFT teams to understand and implement their requirements. You will drive block and full-chip level physical implementation and QOR (power, timing, area). You will develop physical design methodologies, automation scripts and write documentation.
- Drive physical implementation steps including synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, timing closure, CDC analysis and formal verification on blocks, subsystems or full-chip.
- Work with logic designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for physical design closure.
- Perform technical evaluations of vendors, process nodes, IP and provide recommendations.
- Drive physical design methodologies and automation scripts for various implementation steps.
- Help lead project efforts for timing closure of blocks, subsystems and full-chip.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form.