Google

Physical Design Engineer, SoC Static Timing Analysis

Google
Note: By applying to this position you will have an opportunity to share your preferred working location for this position from the following: Haifa, Israel; Tel Aviv-Yafo, Israel
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering or related field or equivalent practical experience.
  • Experience with static timing analysis, including sign-off corner definitions, process margining, interface timing constraints, high-frequency timing convergence and frequency targets setup with technology scaling.
  • Experience in constraints development for sub systems or SOC.

Preferred qualifications:
  • Experience with full-chip static timing analysis, including timing closure.
  • Experience in a scripting language, e.g., Python, Perl, or TCL.
  • Hands-on experience and a solid understanding of ASIC physical design, and physical design flows and methodologies, including synthesis, place and route, static timing analysis, formal verification, and CDC.
  • Working knowledge of semiconductor device physics and transistor characteristics.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.
Responsibilities
  • Drive the sign-off timing convergence for high-performance designs.
  • Set up the timing constraints, define the overall static timing analysis (STA) methodology, set up the STA infrastructure and sign-off convergence flows, and work closely with block owners throughout the project for sign-off timing convergence.
  • Work with logic designers to drive architectural feasibility studies, develop timing, and explore RTL/design trade-offs for physical design closure.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form.